#ifndef MDIO_H_
#define MDIO_H_

#include "xil_types.h"

#define XAE_MDIO_DIV_DFT	29

#define XAE_RST_DEFAULT_TIMEOUT_VAL 1000000

#define REG_MDIO_SETUP      0x44a70500
#define REG_MDIO_CONTROL    0x44a70504
#define REG_MDIO_WRITE_DATA 0x44a70508
#define REG_MDIO_READ_DATA  0x44a7050c

#define XAE_MDIO_MC_MDIOEN_MASK		0x00000040 /**< MII management enable*/

#define XAE_MDIO_MCR_PHYAD_MASK		0x1F000000 /**< Phy Address Mask */
#define XAE_MDIO_MCR_PHYAD_SHIFT	24	   /**< Phy Address Shift */
#define XAE_MDIO_MCR_REGAD_MASK		0x001F0000 /**< Reg Address Mask */
#define XAE_MDIO_MCR_REGAD_SHIFT	16	   /**< Reg Address Shift */
#define XAE_MDIO_MCR_OP_MASK		0x0000C000 /**< Operation Code Mask */
#define XAE_MDIO_MCR_OP_SHIFT		13	   /**< Operation Code Shift */
#define XAE_MDIO_MCR_OP_READ_MASK	0x00008000 /**< Op Code Read Mask */
#define XAE_MDIO_MCR_OP_WRITE_MASK	0x00004000 /**< Op Code Write Mask */
#define XAE_MDIO_MCR_INITIATE_MASK	0x00000800 /**< Ready Mask */
#define XAE_MDIO_MCR_READY_MASK		0x00000080 /**< Ready Mask */

#define EXTERNAL_PHY_ADDR 0x1
#define INTERNAL_PHY_ADDR 0x2

void TriMode_PhySetMdioDivisor(u8 Divisor);
u16 TriMode_PhyRead(u32 PhyAddress, u32 RegisterNum);
void TriMode_PhyWrite(u32 PhyAddress, u32 RegisterNum, u16 PhyData);

void config_SGMII();


#endif /* MDIO_H_ */